Engg Technical notes

1. Introduction In Verilog HDL (Hardware Description Language), designers frequently need to reuse code blocks, perform computations, or model specific behaviors. To achieve modularity and reduce repetitive coding, Verilog provides two procedural constructs: tasks and functions . While both tasks and functions encapsulate reusable code, they serve different purposes : Functions return a single value and execute in zero simulation time . They are ideal for combinational computations . Tasks can handle multiple outputs, include timing control statements (like # , @ , and wait ), and are used in sequential or complex behavioral modeling . This tutorial provides a detailed exploration of tasks and functions, their syntax, usage, examples, and best practices — equipping hardware designers and students to model and simulate Verilog designs effectively. 2. Understanding Tasks in Verilog A task is a procedural block in Verilog that encapsulates code which can be executed mu...

             Understanding Procedural Block Control in Verilog In Verilog, procedural blocks form the foundation for describing behavioral models of hardware. These blocks define how a circuit reacts to inputs over time — enabling both combinational and sequential logic modeling. Procedural blocks become active at simulation time zero and execute when triggered by events or signal changes defined in their sensitivity list . Let’s explore how procedural control works, along with key examples and best coding practices. 🔹 What Are Procedural Blocks? Procedural blocks are code regions that describe behavior rather than structure. They are defined using either of the two keywords: always → executes continuously throughout simulation. initial → executes once at simulation start. These blocks can be controlled using event controls such as level or edge triggers . 🧩 Example 1 – D Latch Using always Block Let’s begin with a basi...

 Continuous Assignment Statements in Verilog In Verilog, continuous assignment statements are used to drive nets (such as wire ). They continuously evaluate the expression on the right-hand side and update the net whenever any input signal changes. These statements are commonly used in combinational circuits , bus systems , and Tri-State buffer designs . Unlike procedural assignments (which execute sequentially inside always or initial blocks), continuous assignments operate concurrently —they always stay active. 🔹 Key Characteristics Continuous assignments drive wire nets directly. Typically used for combinational logic and Tri-State modeling . Declared outside procedural blocks ( always , initial ). They override procedural assignments to the same net. The LHS (left-hand side) must always be a net type , such as wire . Can include delay and drive strength specifications. 🧩 Syntax assign (drive_strength) #(delay) net_name = expression; d...

Looping Statements in Verilog – forever, repeat, while, and for Explained In Verilog , looping statements are used to execute a block of code multiple times , just like in traditional programming languages such as C or Python. However, in Verilog, loops are allowed only inside procedural blocks like initial or always . These loops help designers perform repetitive tasks efficiently — such as generating clocks, testing data, or initializing memories. Let’s explore the four types of looping statements in Verilog with syntax, examples, and clear explanations. 🧩 Types of Looping Statements in Verilog Verilog supports the following four types of loops: forever repeat while for 🟠 1. The forever Loop The forever statement runs continuously without end . As its name suggests, it repeats the block of code indefinitely — until the simulation is manually stopped or a $finish statement is reached. This type of loop is often used in testbenches for generating fr...