Engg Technical notes

1. Why Learn Compiler Directives? Before we even write a line of HDL, let’s answer a simple question: “When the Verilog compiler reads your code, how does it know what to include, what to skip, what constants to use, and how to interpret time?” The answer lies in compiler directives — special preprocessor instructions that guide the compiler before actual synthesis or simulation begins. They don’t create flip‑flops, gates, or signals; instead, they control the environment in which your design is understood and simulated. Think of it this way: Your Verilog compiler is like a translator. Directives are the translator’s instructions : “Before you translate, read this extra file,” “Replace this word everywhere,” “If the designer says debug is on, include extra print statements,” etc. Without these, large designs become unmanageable — hundreds of modules, testbenches, and configurations would be impossible to maintain. 2. The Preprocessor: What Happens Before Compil...

Chapter 1: Introduction to Assertions 1.1 What are Assertions? Definition : Assertions are statements in HDL that check if a design behaves as expected during simulation. They do not change the design behavior , but monitor it. Think of them as automatic examiners : they raise an alert if something goes wrong. Example Analogy: Imagine a traffic light controller. Assertion: “The red and green lights should never be ON at the same time.” If violated, simulation stops or logs a warning. 1.2 Assertion Languages SystemVerilog Assertions (SVA) – built-in assertions in SystemVerilog Open Verification Library (OVL) – a library of reusable assertion modules Property Specification Language (PSL) – industry-standard assertion language 1.3 Advantages of Using Assertions Early Detection of Bugs: Catches design violations during simulation. Self-Checking Testbenches: Reduces manual verification effort. Reusable Verification Components: Assertion...

1. Introduction to Logic Synthesis Logic synthesis is the process of converting high-level hardware descriptions into gate-level implementations that can be physically realized on silicon (ASICs) or programmable devices (FPGAs). In simpler words: Logic synthesis translates your Verilog or VHDL code into a network of logic gates and flip-flops that can be physically built. 1.1. Life Before HDL and Synthesis Before hardware description languages (HDL) like Verilog: Engineers manually designed circuits using logic diagrams or schematics . Large designs were error-prone, difficult to modify, and time-consuming to implement. Optimizing gate count or timing was extremely hard. Challenges: Reusing a module in multiple projects was labor-intensive. Making changes in design required redrawing entire schematics. Verification and debugging were manual and slow. 1.2. Impact of HDL and Logic Synthesis With HDL and synthesis: Designers write behavioral or stru...

 Continuous Assignment Statements in Verilog In Verilog, continuous assignment statements are used to drive nets (such as wire ). They continuously evaluate the expression on the right-hand side and update the net whenever any input signal changes. These statements are commonly used in combinational circuits , bus systems , and Tri-State buffer designs . Unlike procedural assignments (which execute sequentially inside always or initial blocks), continuous assignments operate concurrently —they always stay active. 🔹 Key Characteristics Continuous assignments drive wire nets directly. Typically used for combinational logic and Tri-State modeling . Declared outside procedural blocks ( always , initial ). They override procedural assignments to the same net. The LHS (left-hand side) must always be a net type , such as wire . Can include delay and drive strength specifications. 🧩 Syntax assign (drive_strength) #(delay) net_name = expression; d...