Verilog 11 : Looping Statements in Verilog

Looping Statements in Verilog – forever, repeat, while, and for Explained

In Verilog, looping statements are used to execute a block of code multiple times, just like in traditional programming languages such as C or Python.
However, in Verilog, loops are allowed only inside procedural blocks like initial or always.

These loops help designers perform repetitive tasks efficiently — such as generating clocks, testing data, or initializing memories.

Let’s explore the four types of looping statements in Verilog with syntax, examples, and clear explanations.

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🧩 Types of Looping Statements in Verilog

Verilog supports the following four types of loops:

1. forever

2. repeat

3. while

4. for

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🟠 1. The forever Loop

The forever statement runs continuously without end.
As its name suggests, it repeats the block of code indefinitely — until the simulation is manually stopped or a $finish statement is reached.

This type of loop is often used in testbenches for generating free-running clocks or signals that toggle forever.

🔧 Syntax:

forever <statement>;

⚠️ Caution:
If there’s no timing control (like #delay, @event, or wait) inside a forever loop, the simulation will hang because it never yields time.

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💡 Example – Free Running Clock Generator

module forever_example ();
  reg clk;

  initial begin
    #1 clk = 0; 
    forever begin
      #5 clk = !clk; 
    end
  end 

  initial begin
    $monitor ("Time = %d  clk = %b", $time, clk);
    #100 $finish;
  end
endmodule

🧠 Explanation:

• The clk signal toggles every 5 time units.

• The loop runs infinitely, generating a continuous clock signal.

• The simulation ends after 100 time units due to $finish.

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🟢 2. The repeat Loop

The repeat statement executes a block of code a fixed number of times.
It is perfect when you know exactly how many iterations are required — such as performing a rotation, shifting bits, or generating test vectors.

🔧 Syntax:

repeat (<number>) <statement>;

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💡 Example – Repeat Loop

module repeat_example();
  reg [3:0] opcode;
  reg [15:0] data;
  reg temp;

  always @ (opcode or data) begin
    if (opcode == 10) begin
      // Perform rotate operation 8 times
      repeat (8) begin 
        #1 temp = data[15];
        data = data << 1;
        data[0] = temp;   
      end 
    end
  end

  // Simple test code
  initial begin
    $display ("TEMP   DATA");
    $monitor ("%b     %b", temp, data);
    #1 data = 16'hF0;
    #1 opcode = 10;
    #10 opcode = 0;
    #1 $finish;
  end
endmodule

🧠 Explanation:

• The loop runs exactly 8 times when opcode == 10.

• Each iteration shifts data left by one bit, creating a rotating effect.

• Useful for testing and debugging small logic blocks.

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🔵 3. The while Loop

The while loop continues execution as long as the given expression is true.
Once the condition becomes false, the loop terminates automatically.

This structure is similar to while loops in software programming and is ideal for conditional iteration.

🔧 Syntax:

while (<expression>) <statement>;

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💡 Example – While Loop

module while_example();
  reg [5:0] loc;
  reg [7:0] data;

  always @ (data or loc) begin
    loc = 0;
    // If data is zero, location becomes invalid (32)
    if (data == 0) begin
      loc = 32;
    end else begin
      while (data[0] == 0) begin
        loc = loc + 1;
        data = data >> 1;
      end
    end 
    $display ("DATA = %b   LOCATION = %d", data, loc);
  end

  initial begin
    #1 data = 8'b11;
    #1 data = 8'b100;
    #1 data = 8'b1000;
    #1 data = 8'b1000_0000;
    #1 data = 8'b0;
    #1 $finish;
  end
endmodule

🧠 Explanation:

• The loop shifts data right until the least significant bit (LSB) becomes 1.

• The variable loc counts how many times the shift occurred.

• When data is 0, it assigns loc = 32 (invalid).

• Demonstrates dynamic looping based on runtime conditions.

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🟣 4. The for Loop

The for statement is the most commonly used loop in Verilog and works just like in traditional programming languages.

It executes:

1. An initial assignment once at the start.

2. A test condition before each iteration.

3. A step assignment at the end of each iteration.

⚠️ Note: Verilog does not support the ++ or -- operators found in C. Use i = i + 1 instead.

🔧 Syntax:

for (<initial assignment>; <expression>; <step assignment>)
  <statement>;

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💡 Example – For Loop

module for_example();
  integer i;
  reg [7:0] ram [0:255];

  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      #1 $display("Address = %g  Data = %h", i, ram[i]);
      ram[i] <= 0; // Initialize the RAM with 0
      #1 $display("Address = %g  Data = %h", i, ram[i]);
    end
    #1 $finish;
  end
endmodule

🧠 Explanation:

• The loop iterates from 0 to 255, initializing a 256-byte memory (RAM) to 0.

• Displays address and data before and after initialization.

• This is one of the most common applications of for loops in Verilog testbenches.

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⚡ Comparison of Verilog Looping Statements

Loop Type	Condition	Typical Use	Terminates Automatically	Requires Timing Control?
forever	None	Clock generation, waveform repetition	❌ No	✅ Yes
repeat	Fixed count	Bit rotations, test iterations	✅ Yes	Optional
while	Expression-based	Conditional shifting or scanning	✅ Yes	Optional
for	Initialization + Condition + Step	Memory initialization, repetitive testing	✅ Yes	Optional

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✨ Summary

• forever – Used for continuous processes like clock generation.

• repeat – Executes a statement a fixed number of times.

• while – Loops while a condition is true (dynamic iteration).

• for – Performs repetitive tasks with initialization and step updates.

Understanding these looping statements is essential for writing efficient testbenches, automation routines, and verification scripts in Verilog.

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