VERILOG : 2. HDL Syntax & Semantics: [Understanding Basic Lexical Conventions in Verilog HDL]
Understanding Basic Lexical Conventions in Verilog HDL When learning Verilog Hardware Description Language (HDL), it’s essential to begin with the basic lexical conventions , as these form the foundation for writing clean, correct, and maintainable code. Interestingly, many of these conventions are similar to those in the C programming language, but with Verilog-specific rules. In this blog, we’ll explore whitespace , comments , case sensitivity , identifiers , escaped identifiers , and number formats in Verilog HDL, complete with good and bad examples. 1. White Space in Verilog White space characters in Verilog are mostly ignored except when they are needed to separate tokens. However, inside strings, they are significant. White space characters include: - Blank spaces - Tabs - Carriage returns - New-lines - Form-feeds Example: Good vs. Bad Code ❌ Bad Code: module addbit(a,b,ci,sum,co); input a,b,ci;output sum co; wire a,b,ci,sum,co;endmodule ✅ Good Code...