Engg Technical notes

Chapter 1: Introduction to Assertions 1.1 What are Assertions? Definition : Assertions are statements in HDL that check if a design behaves as expected during simulation. They do not change the design behavior , but monitor it. Think of them as automatic examiners : they raise an alert if something goes wrong. Example Analogy: Imagine a traffic light controller. Assertion: “The red and green lights should never be ON at the same time.” If violated, simulation stops or logs a warning. 1.2 Assertion Languages SystemVerilog Assertions (SVA) – built-in assertions in SystemVerilog Open Verification Library (OVL) – a library of reusable assertion modules Property Specification Language (PSL) – industry-standard assertion language 1.3 Advantages of Using Assertions Early Detection of Bugs: Catches design violations during simulation. Self-Checking Testbenches: Reduces manual verification effort. Reusable Verification Components: Assertion...

1. Introduction to Logic Synthesis Logic synthesis is the process of converting high-level hardware descriptions into gate-level implementations that can be physically realized on silicon (ASICs) or programmable devices (FPGAs). In simpler words: Logic synthesis translates your Verilog or VHDL code into a network of logic gates and flip-flops that can be physically built. 1.1. Life Before HDL and Synthesis Before hardware description languages (HDL) like Verilog: Engineers manually designed circuits using logic diagrams or schematics . Large designs were error-prone, difficult to modify, and time-consuming to implement. Optimizing gate count or timing was extremely hard. Challenges: Reusing a module in multiple projects was labor-intensive. Making changes in design required redrawing entire schematics. Verification and debugging were manual and slow. 1.2. Impact of HDL and Logic Synthesis With HDL and synthesis: Designers write behavioral or stru...

1. Introduction In Verilog HDL (Hardware Description Language), designers frequently need to reuse code blocks, perform computations, or model specific behaviors. To achieve modularity and reduce repetitive coding, Verilog provides two procedural constructs: tasks and functions . While both tasks and functions encapsulate reusable code, they serve different purposes : Functions return a single value and execute in zero simulation time . They are ideal for combinational computations . Tasks can handle multiple outputs, include timing control statements (like # , @ , and wait ), and are used in sequential or complex behavioral modeling . This tutorial provides a detailed exploration of tasks and functions, their syntax, usage, examples, and best practices — equipping hardware designers and students to model and simulate Verilog designs effectively. 2. Understanding Tasks in Verilog A task is a procedural block in Verilog that encapsulates code which can be executed mu...

When we think of Verilog , most engineers picture RTL (Register Transfer Level) coding – writing always blocks, designing with if-else or case statements, and abstracting digital logic into behavioral or dataflow descriptions. However, Verilog also provides a lower-level way of modeling hardware, called Gate-Level Modeling . This is where you describe your circuits directly in terms of logic gates , switches , and transistor-level primitives . Even though gate-level coding is rarely used in RTL design , it plays a vital role after synthesis in ASIC and FPGA design flows . Let’s break it down. 🔑 Why Gate-Level Modeling Matters RTL Coding → Synthesis → Gate-Level Netlist In real chip design, RTL code is synthesized into logic gates . The synthesis tool generates a Verilog netlist made of gate primitives and standard cells . Gate-Level Simulation (GLS) This netlist is then simulated (often with back-annotated timing from an SDF file ) to check how the design behaves w...