Engg Technical notes

1. Introduction In Verilog HDL (Hardware Description Language), designers frequently need to reuse code blocks, perform computations, or model specific behaviors. To achieve modularity and reduce repetitive coding, Verilog provides two procedural constructs: tasks and functions . While both tasks and functions encapsulate reusable code, they serve different purposes : Functions return a single value and execute in zero simulation time . They are ideal for combinational computations . Tasks can handle multiple outputs, include timing control statements (like # , @ , and wait ), and are used in sequential or complex behavioral modeling . This tutorial provides a detailed exploration of tasks and functions, their syntax, usage, examples, and best practices — equipping hardware designers and students to model and simulate Verilog designs effectively. 2. Understanding Tasks in Verilog A task is a procedural block in Verilog that encapsulates code which can be executed mu...

 Continuous Assignment Statements in Verilog In Verilog, continuous assignment statements are used to drive nets (such as wire ). They continuously evaluate the expression on the right-hand side and update the net whenever any input signal changes. These statements are commonly used in combinational circuits , bus systems , and Tri-State buffer designs . Unlike procedural assignments (which execute sequentially inside always or initial blocks), continuous assignments operate concurrently —they always stay active. 🔹 Key Characteristics Continuous assignments drive wire nets directly. Typically used for combinational logic and Tri-State modeling . Declared outside procedural blocks ( always , initial ). They override procedural assignments to the same net. The LHS (left-hand side) must always be a net type , such as wire . Can include delay and drive strength specifications. 🧩 Syntax assign (drive_strength) #(delay) net_name = expression; d...

When we think of Verilog , most engineers picture RTL (Register Transfer Level) coding – writing always blocks, designing with if-else or case statements, and abstracting digital logic into behavioral or dataflow descriptions. However, Verilog also provides a lower-level way of modeling hardware, called Gate-Level Modeling . This is where you describe your circuits directly in terms of logic gates , switches , and transistor-level primitives . Even though gate-level coding is rarely used in RTL design , it plays a vital role after synthesis in ASIC and FPGA design flows . Let’s break it down. 🔑 Why Gate-Level Modeling Matters RTL Coding → Synthesis → Gate-Level Netlist In real chip design, RTL code is synthesized into logic gates . The synthesis tool generates a Verilog netlist made of gate primitives and standard cells . Gate-Level Simulation (GLS) This netlist is then simulated (often with back-annotated timing from an SDF file ) to check how the design behaves w...