Posts

Showing posts with the label memory modelling and fsm

Verilog 15 :Memory Modeling and Finite State Machines (FSMs)

Image
1. Introduction to Sequential Logic Before we dive into memories and FSMs, we need to understand sequential logic . Combinational logic : output depends only on current inputs . Examples: adders, multiplexers, logic gates. Sequential logic : output depends on current inputs and previous state . Examples: flip-flops, registers, counters. Key Building Blocks: Flip-flops : Store a single bit of data. Types include D, T, JK flip-flops . Registers : Group of flip-flops storing multiple bits. Clock signal : Controls when sequential elements update their state. Why Sequential Logic Matters: Memories and FSMs are sequential circuits. Without understanding how data flows over time (clock cycles), modeling these components becomes impossible. 2. Memory Modeling in Verilog Memory in digital systems is simply a collection of registers or arrays of storage elements . 2.1. Memory Basics Memory Address : Unique location index (like 0, 1, 2, …). Memory Word : Data s...