Verilog 12 : Continuous Assignment Statements in Verilog

 Continuous Assignment Statements in Verilog

In Verilog, continuous assignment statements are used to drive nets (such as wire). They continuously evaluate the expression on the right-hand side and update the net whenever any input signal changes.

These statements are commonly used in combinational circuits, bus systems, and Tri-State buffer designs. Unlike procedural assignments (which execute sequentially inside always or initial blocks), continuous assignments operate concurrently—they always stay active.

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🔹 Key Characteristics

• Continuous assignments drive wire nets directly.

• Typically used for combinational logic and Tri-State modeling.

• Declared outside procedural blocks (always, initial).

• They override procedural assignments to the same net.

• The LHS (left-hand side) must always be a net type, such as wire.

• Can include delay and drive strength specifications.

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🧩 Syntax

assign (drive_strength) #(delay) net_name = expression;

• drive_strength → optional; defines signal strength.

• delay → optional; models propagation delay.

• expression → defines how the output depends on inputs.

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💡 Example 1 – Half Adder Using Continuous Assignment

Let’s begin with a simple Half Adder modeled using continuous assignments.

module half_adder_assign();
  reg a, b;
  wire sum, carry;

  // Continuous assignment for combinational logic
  assign sum = a ^ b;
  assign carry = a & b;

  initial begin
    $monitor("TIME=%0t | A=%b | B=%b | SUM=%b | CARRY=%b", $time, a, b, sum, carry);
    a = 0; b = 0;
    #5 a = 1;
    #5 b = 1;
    #5 a = 0;
    #5 $finish;
  end
endmodule

🧠 Explanation:
Here, the assign keyword continuously monitors changes in a or b and updates sum and carry instantly. This is ideal for simple combinational circuits.

📂 File: half_adder_assign.v

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💡 Example 2 – Tri-State Buffer Using assign

A Tri-State buffer allows a signal to be sent to a shared line only when enabled. When disabled, it disconnects (high-impedance Z state). Let’s see how to model this.

module tri_state_buffer();
  reg data_in, enable;
  wire data_out;

  // Tri-state modeling using conditional continuous assignment
  assign data_out = enable ? data_in : 1'bz;

  initial begin
    $monitor("TIME=%0t | ENABLE=%b | DATA_IN=%b | DATA_OUT=%b", $time, enable, data_in, data_out);
    enable = 0; data_in = 0;
    #5 data_in = 1;
    #5 enable = 1;
    #5 data_in = 0;
    #5 enable = 0;
    #5 $finish;
  end
endmodule

🧠 Explanation:

• When enable = 1, data_out follows data_in.

• When enable = 0, output becomes high-impedance (Z).
  This mimics real Tri-State buffer behavior used in bus systems.

📂 File: tri_state_buffer.v

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⏱️ Propagation Delay in Continuous Assignment

Continuous assignments can simulate propagation delay, which represents how long a real gate takes to produce output after input changes. You can specify a single delay or a min:typ:max delay range.

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💡 Example 3 – Tri-State Buffer with Delays

module tri_state_with_delay();
  reg data_in, enable;
  wire data_out;

  // Delay modeling: #(min:typ:max)
  assign #(2:4:6) data_out = enable ? data_in : 1'bz;

  initial begin
    $monitor("TIME=%0t | ENABLE=%b | DATA_IN=%b | DATA_OUT=%b", $time, enable, data_in, data_out);
    enable = 0; data_in = 0;
    #5 data_in = 1;
    #5 enable = 1;
    #5 data_in = 0;
    #5 enable = 0;
    #5 $finish;
  end
endmodule

🧠 Explanation:

• The delay of (2:4:6) means:

  • Minimum delay = 2 time units

  • Typical delay = 4 time units

  • Maximum delay = 6 time units
    This helps in timing analysis and realistic simulation of digital circuits.

📂 File: tri_state_with_delay.v

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⚡ Quick Comparison

Feature	Description
Purpose	Drive wire nets continuously
Used For	Combinational logic, Tri-State buffers
Location	Outside procedural blocks
Delay Support	Yes, supports single or range delay
LHS Type	Must be net (e.g., wire)
Behavior	Executes concurrently, always active

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🧭 Conclusion

Continuous assignment statements are the core of structural modeling in Verilog.
They ensure signal updates happen automatically, providing an accurate representation of hardware wiring. Whether you’re designing logic gates or simulating real-world delays, assign statements make your Verilog code both elegant and efficient.

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