Engg Technical notes

1. Introduction In Verilog HDL (Hardware Description Language), designers frequently need to reuse code blocks, perform computations, or model specific behaviors. To achieve modularity and reduce repetitive coding, Verilog provides two procedural constructs: tasks and functions . While both tasks and functions encapsulate reusable code, they serve different purposes : Functions return a single value and execute in zero simulation time . They are ideal for combinational computations . Tasks can handle multiple outputs, include timing control statements (like # , @ , and wait ), and are used in sequential or complex behavioral modeling . This tutorial provides a detailed exploration of tasks and functions, their syntax, usage, examples, and best practices — equipping hardware designers and students to model and simulate Verilog designs effectively. 2. Understanding Tasks in Verilog A task is a procedural block in Verilog that encapsulates code which can be executed mu...

Looping Statements in Verilog – forever, repeat, while, and for Explained In Verilog , looping statements are used to execute a block of code multiple times , just like in traditional programming languages such as C or Python. However, in Verilog, loops are allowed only inside procedural blocks like initial or always . These loops help designers perform repetitive tasks efficiently — such as generating clocks, testing data, or initializing memories. Let’s explore the four types of looping statements in Verilog with syntax, examples, and clear explanations. 🧩 Types of Looping Statements in Verilog Verilog supports the following four types of loops: forever repeat while for 🟠 1. The forever Loop The forever statement runs continuously without end . As its name suggests, it repeats the block of code indefinitely — until the simulation is manually stopped or a $finish statement is reached. This type of loop is often used in testbenches for generating fr...

 The Conditional Statement in Verilog: if-else, case, casex, and casez Explained In digital design, conditional statements are the backbone of decision-making in hardware description languages like Verilog . They control the flow of execution in your code, determining which set of statements should execute when certain conditions are met. In this post, we’ll explore the if-else , nested if , parallel if , and case statements — including their special forms casez and casex — with clear syntax, examples, and simulation outputs. 🔹 Understanding Conditional Statements in Verilog Conditional statements help you control when and how certain parts of your Verilog code execute. These are mainly used inside procedural blocks such as always or initial . The key conditional statements are: if and if-else nested if-else parallel if case , casez , and casex ⚙️ 1. The if-else Statement in Verilog The if-else statement is used to make decisions based on conditi...