VERILOG : 2. HDL Syntax & Semantics: [Understanding Basic Lexical Conventions in Verilog HDL]

 Understanding Basic Lexical Conventions in Verilog HDL

When learning Verilog Hardware Description Language (HDL), it’s essential to begin with the basic lexical conventions, as these form the foundation for writing clean, correct, and maintainable code. Interestingly, many of these conventions are similar to those in the C programming language, but with Verilog-specific rules.

In this blog, we’ll explore whitespace, comments, case sensitivity, identifiers, escaped identifiers, and number formats in Verilog HDL, complete with good and bad examples.

1. White Space in Verilog

White space characters in Verilog are mostly ignored except when they are needed to separate tokens. However, inside strings, they are significant.

White space characters include:
- Blank spaces
- Tabs
- Carriage returns
- New-lines
- Form-feeds

Example: Good vs. Bad Code

❌ Bad Code:

module addbit(a,b,ci,sum,co);
input a,b,ci;output sum co;
wire a,b,ci,sum,co;endmodule

✅ Good Code:

module addbit (
    a,
    b,
    ci,
    sum,
    co
);
    input  a;
    input  b;
    input  ci;
    output sum;
    output co;

    wire   a;
    wire   b;
    wire   ci;
    wire   sum;
    wire   co;

endmodule

2. Comments in Verilog

Like C, Verilog supports single-line and multi-line comments.

- Single-line comments: Start with // and continue until the end of the line.
- Multi-line comments: Begin with /* and end with */.

✅ Good Code:

/* This is a
   Multi-line comment example */
module addbit (
    a,
    b,
    ci,
    sum,
    co
);

// Input Ports
input  a;
input  b;
input  ci;

// Output Ports
output sum;
output co;

// Data Types
wire   a;
wire   b;
wire   ci;
wire   sum;
wire   co;

endmodule

3. Case Sensitivity

Verilog is case-sensitive.
- Lowercase and uppercase versions of the same word are treated as different identifiers.
- All Verilog keywords are lowercase.

✅ Good Code:

input    // Verilog keyword
wire     // Verilog keyword
WIRE     // Valid unique name (not a keyword)
Wire     // Valid unique name (not a keyword)

4. Identifiers

Identifiers are names given to objects such as modules, registers, or functions.

Rules for Identifiers:
- Must start with an alphabet or underscore (a-z, A-Z, _)
- May contain letters, digits, underscores (_), or dollar signs ($)
- Can be up to 1024 characters long

✅ Good Code:

data_input
clk_input
my$clk
i386
A

Escaped Identifiers

If you want to use special characters in an identifier, you can use escaped identifiers.

Rules:
- Start with a backslash (\)
- End with a whitespace
- Without whitespace, the identifier won’t terminate properly

✅ Good Code:

module \1dff (
    q,      // Q output
    \q~ ,   // Q_out output
    d,      // D input
    cl$k,   // Clock input
    \reset* // Reset input
);

input d, cl$k, \reset* ;
output q, \q~ ;

endmodule

5. Numbers in Verilog

Verilog supports decimal, hexadecimal, octal, and binary numbers, with options for signed or unsigned.

Integer Numbers:
- Default size: 32 bits (unsized)
- Format: <size>'<radix><value>
- Radix: b = binary, o = octal, d = decimal, h = hexadecimal

Expansion Rule:
- If size > value → leftmost bits are filled
- If size < value → leftmost bits are truncated

✅ Good Code:

1           // 32-bit integer
8'hAA       // Hexadecimal: 10101010
6'b10_0011  // Binary: 100011
'hF         // Hexadecimal: 000...1111

A. Real Numbers

Real numbers can be written in decimal or scientific notation.
- Cannot contain X or Z
- Rounded when assigned to an integer

✅ Good Code:

1.2
0.6
3.5E6

B. Signed vs. Unsigned Numbers

Unsigned: Numbers without a - sign
Signed: Negative numbers use two’s complement format
Use 'signed' keyword for signed arithmetic

✅ Good Code:

module signed_number;

    reg [31:0] a;

    initial begin
        a = 14'h1234;
        $display ("Current Value of a = %h", a);

        a = -14'h1234;
        $display ("Current Value of a = %h", a);

        a = 32'hDEAD_BEEF;
        $display ("Current Value of a = %h", a);

        a = -32'hDEAD_BEEF;
        $display ("Current Value of a = %h", a);

        #10 $finish;
    end

endmodule

Conclusion

The basic lexical conventions in Verilog HDL—white space, comments, case sensitivity, identifiers, escaped identifiers, and number formats—are the foundation of writing clean and error-free code.

By following these rules:
- Your code will be easier to read and debug
- You’ll avoid syntax-related pitfalls
- You’ll write Verilog that’s professional and industry-ready

📌 Coming Next: We’ll begin a new chapter series on Verilog HDL, exploring modules, data types, and procedural blocks step by step. Stay tuned!