Engg Technical notes

1. Introduction to Sequential Logic Before we dive into memories and FSMs, we need to understand sequential logic . Combinational logic : output depends only on current inputs . Examples: adders, multiplexers, logic gates. Sequential logic : output depends on current inputs and previous state . Examples: flip-flops, registers, counters. Key Building Blocks: Flip-flops : Store a single bit of data. Types include D, T, JK flip-flops . Registers : Group of flip-flops storing multiple bits. Clock signal : Controls when sequential elements update their state. Why Sequential Logic Matters: Memories and FSMs are sequential circuits. Without understanding how data flows over time (clock cycles), modeling these components becomes impossible. 2. Memory Modeling in Verilog Memory in digital systems is simply a collection of registers or arrays of storage elements . 2.1. Memory Basics Memory Address : Unique location index (like 0, 1, 2, …). Memory Word : Data s...

1. Introduction In Verilog HDL (Hardware Description Language), designers frequently need to reuse code blocks, perform computations, or model specific behaviors. To achieve modularity and reduce repetitive coding, Verilog provides two procedural constructs: tasks and functions . While both tasks and functions encapsulate reusable code, they serve different purposes : Functions return a single value and execute in zero simulation time . They are ideal for combinational computations . Tasks can handle multiple outputs, include timing control statements (like # , @ , and wait ), and are used in sequential or complex behavioral modeling . This tutorial provides a detailed exploration of tasks and functions, their syntax, usage, examples, and best practices — equipping hardware designers and students to model and simulate Verilog designs effectively. 2. Understanding Tasks in Verilog A task is a procedural block in Verilog that encapsulates code which can be executed mu...

             Understanding Procedural Block Control in Verilog In Verilog, procedural blocks form the foundation for describing behavioral models of hardware. These blocks define how a circuit reacts to inputs over time — enabling both combinational and sequential logic modeling. Procedural blocks become active at simulation time zero and execute when triggered by events or signal changes defined in their sensitivity list . Let’s explore how procedural control works, along with key examples and best coding practices. 🔹 What Are Procedural Blocks? Procedural blocks are code regions that describe behavior rather than structure. They are defined using either of the two keywords: always → executes continuously throughout simulation. initial → executes once at simulation start. These blocks can be controlled using event controls such as level or edge triggers . 🧩 Example 1 – D Latch Using always Block Let’s begin with a basi...

 Continuous Assignment Statements in Verilog In Verilog, continuous assignment statements are used to drive nets (such as wire ). They continuously evaluate the expression on the right-hand side and update the net whenever any input signal changes. These statements are commonly used in combinational circuits , bus systems , and Tri-State buffer designs . Unlike procedural assignments (which execute sequentially inside always or initial blocks), continuous assignments operate concurrently —they always stay active. 🔹 Key Characteristics Continuous assignments drive wire nets directly. Typically used for combinational logic and Tri-State modeling . Declared outside procedural blocks ( always , initial ). They override procedural assignments to the same net. The LHS (left-hand side) must always be a net type , such as wire . Can include delay and drive strength specifications. 🧩 Syntax assign (drive_strength) #(delay) net_name = expression; d...