VERILOG 9 :Abstraction Levels and Procedural Blocks

Verilog HDL (Hardware Description Language) is widely used for modeling digital systems. It allows designers to describe circuits at different levels of abstraction, making it easier to go from high-level behavior to gate-level implementation. In this guide, we’ll explore these abstraction levels, procedural blocks, and important Verilog constructs with practical examples.

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Abstraction Levels in Verilog

Verilog supports multiple modeling styles depending on the level of detail required:

1. Behavioral Modeling

   • Describes the functionality of the design rather than its structure.

   • Suitable for quick prototyping.

   • Example: writing algorithms for counters, FSMs, or arithmetic operations.

2. RTL (Register Transfer Level) Modeling

   • Describes the design in terms of data flow between registers and logic.

   • Mostly used for synthesis into hardware.

3. Structural Modeling

   • Describes how gates, flip-flops, and modules are interconnected.

   • Used for low-level representation, close to actual hardware.

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Procedural Blocks in Verilog

Verilog allows behavioral code to be written inside procedural blocks.
There are two main types:

• initial block

  • Executes only once at simulation start (time = 0).

  • Commonly used for testbench stimulus or initial conditions.

• always block

  • Executes continuously whenever its sensitivity condition is met.

  • Commonly used for sequential and combinational logic.

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Example: initial Block

module initial_example();
  reg clk, reset, enable, data;

  initial begin
    clk = 0;
    reset = 0;
    enable = 0;
    data = 0;
  end
endmodule

Here, all signals are initialized only once at the start of simulation.

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Example: always Block

module always_example();
  reg clk, reset, enable, q_in, data;

  always @(posedge clk)
    if (reset)
      data <= 0;
    else if (enable)
      data <= q_in;
endmodule

This block executes on every rising edge of clk, updating the register accordingly.

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Procedural Assignments in Verilog

• Allowed on: reg, integer, time, real types.

• Not allowed on: wire (nets).

• Assignments can be:

  • Blocking (=) – executed sequentially.

  • Nonblocking (<=) – executed in parallel.

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Blocking vs Nonblocking Example

module blocking_nonblocking();
  reg a, b;

  initial begin
    a = 0;   // blocking
    b <= 1;  // nonblocking
  end
endmodule

👉 Tip:

• Use blocking (=) inside combinational logic.

• Use nonblocking (<=) inside sequential logic (flip-flops).

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Statement Groups: begin-end and fork-join

When multiple statements are needed inside a block, Verilog provides grouping constructs:

• Sequential (begin ... end) – executes one after another.

• Parallel (fork ... join) – executes all statements simultaneously.

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Example: Sequential Block

initial begin
  #1 clk = 0;
  #10 reset = 0;
  #5 enable = 0;
  #3 data = 0;
end

Statements run one after another → total delay accumulates.

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Example: Parallel Block

initial fork
  #1 clk = 0;
  #10 reset = 0;
  #5 enable = 0;
  #3 data = 0;
join

Here, assignments happen in parallel, each after its specified delay.

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Continuous Assignments with assign-deassign and force-release

Apart from normal procedural assignments, Verilog also supports temporary continuous assignments:

1. assign and deassign

   • Used to override procedural assignments temporarily.

   • Can only be applied to registers (reg).

2. force and release

   • Stronger than assign/deassign.

   • Can be applied to both reg and wire.

   • Useful for debugging or injecting errors during simulation.

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Example: Force and Release

always @(preset)
  if (preset)
    force U.q = 1;   // force assignment
  else
    release U.q;     // release control

This allows direct control over a signal, bypassing its normal behavior, until released.

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Key Takeaways

• Verilog supports three abstraction levels: Behavioral, RTL, and Structural.

• initial block runs once, always block runs continuously.

• Use blocking (=) for sequential execution, nonblocking (<=) for parallel updates.

• begin-end → sequential grouping; fork-join → parallel grouping.

• assign/deassign and force/release allow overriding signals for special conditions.