VERILOG : 7. User Defined Primitives (UDPs)

🔹 What are User Defined Primitives (UDPs)?

In Verilog, User Defined Primitives (UDPs) are a way to create custom logic primitives beyond the limited set of built-in primitives. They allow designers to define combinational logic or sequential logic using truth tables.

👉 In simple words, UDPs are custom truth tables written in Verilog.

For example:

• Combinational UDP → Works like a simple gate (AND, OR, XOR, etc.) but defined by the user.

• Sequential UDP → Models latches, flip-flops, and other memory elements.

These are particularly useful when modeling ASIC libraries or verifying custom-designed hardware components.

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🔹 Syntax of a UDP

Every UDP in Verilog follows a strict syntax:

primitive udp_name (output, input1, input2, ...);
   output <output_port>;
   input <input_port(s)>;
   reg <output_port>;   // Only required for sequential UDP

   // Optional initialization
   initial <output_port> = <init_value>;

   table
      <input_condition> : <output_value> ;
   endtable
endprimitive

Example UDP Skeleton:

primitive udp_syntax (a, b, c, d);
   output a;
   input b, c, d;

   // Functionality defined inside table
   table
      // truth table goes here
   endtable
endprimitive

Here:

• primitive → Keyword to define UDP.

• a → Output port (must always come first).

• b, c, d → Input ports.

• table ... endtable → Defines functionality.

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🔹 Rules for UDP Ports

When defining UDPs, some strict rules apply:

1. ✅ A UDP can only have one output but up to 10 inputs.

2. ✅ The output port must be the first port in the list.

3. ✅ All ports are scalar (vectors are not allowed).

4. ✅ UDPs cannot have bidirectional ports (inout).

5. ✅ For sequential UDPs, the output must be declared as a reg.

6. ❌ Declaring reg for combinational UDP outputs is illegal.

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🔹 Combinational UDP Example

Let’s define a simple OR gate using UDP:

primitive udp_body (a, b, c);
   output a;
   input b, c;

   table
      // b  c : a
         ?  1 : 1;
         1  ? : 1;
         0  0 : 0;
   endtable
endprimitive

Explanation:

• ? means “don’t care” (0, 1, or x).

• If c is 1, output is 1.

• If b is 1, output is 1.

• If both are 0, output is 0.

This behaves just like a logical OR gate.

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🔹 Testbench for Combinational UDP

To test the above UDP, we can write a simple testbench:

`include "udp_body.v"

module udp_body_tb();
   reg b, c;
   wire a;

   udp_body udp (a, b, c);

   initial begin
      $monitor("B = %b, C = %b => A = %b", b, c, a);
      b = 0; c = 0;
      #1 b = 1;
      #1 b = 0; c = 1;
      #1 b = 1; c = 1;
      #1 b = 1'bx;
      #1 c = 1'bx;
      #1 $finish;
   end
endmodule

Sample Output:

B = 0, C = 0 => A = 0
B = 1, C = 0 => A = 1
B = 0, C = 1 => A = 1
B = 1, C = 1 => A = 1
B = x, C = 1 => A = 1
B = x, C = 0 => A = x

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🔹 Sequential UDP Example

Sequential UDPs behave like flip-flops or latches.

Example: A UDP with an initial state:

primitive udp_initial (a, b, c);
   output a;
   input b, c;
   reg a;

   // Initialize output
   initial a = 1'b1;

   table
      // define sequential behavior here
   endtable
endprimitive

Here, reg a; is necessary since it stores state.

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🔹 UDP Symbols Used in Tables

Verilog UDPs use special symbols in truth tables:

Symbol	Meaning	Example
?	Don’t care (0, 1, or x)	? 1 : 1;
b	0 or 1 (not x)	b ? : 1;
r	Rising edge (0 → 1)	(01)
f	Falling edge (1 → 0)	(10)
p	Positive edge (including x and z cases)	(0x), (x1)
n	Negative edge (including x and z cases)	(1x), (x0)
*	Any transition	(??)
-	No change in output	Used in sequential UDPs

⚠️ Note: z is not allowed in UDP input tables.

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🔹 Why Use UDPs?

UDPs are useful when:

• You want to model custom primitives for ASIC libraries.

• You need a simplified abstraction of a logic function.

• You’re building sequential elements without writing long always blocks.

• You want to simulate and verify custom hardware more efficiently.

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🔹 Final Thoughts

User Defined Primitives (UDPs) in Verilog give hardware designers the ability to go beyond built-in gates and model custom logic with ease. With the help of tables, you can define combinational and sequential behaviors concisely.

By mastering UDPs, you can:

• Build accurate ASIC models

• Simplify simulation code

• Improve testbench readability

👉 Whether you’re a beginner or an advanced designer, UDPs are an essential part of mastering Verilog HDL.