VERILOG : 3. Modules in Verilog

Modules in Verilog – The Building Blocks of Digital Design

When designing hardware in Verilog, everything revolves around modules. Think of a module as a blueprint or block that describes a piece of your circuit. Just like LEGO bricks, modules can be put together to build bigger systems.

In this blog, we’ll explore what modules are, how ports connect them, examples of instantiation, and common rules to follow when using them.

---

What is a Module?

• A module is the fundamental building block of Verilog designs.

• Every Verilog design is made up of one or more modules, which may represent anything from a simple gate to a full processor.

• You can instantiate a module inside another module, creating a design hierarchy.

Example:

• A half adder can be one module.

• A full adder can be built by instantiating two half adders.

• An adder array can be built by instantiating multiple full adders.

This modular approach keeps designs clean and scalable.

---

Ports – Communicating with the Outside World

Modules interact with their environment using ports.

• Input ports → Signals coming into the module.

• Output ports → Signals going out of the module.

• Inout ports → Bi-directional signals (e.g., data buses).

Port Declaration Syntax:

input  [range] port_name;
output [range] port_name;
inout  [range] port_name;

Good practice: declare one port per line for clarity.

Example:

input        clk;       // Clock input
input  [15:0] data_in;  // 16-bit input bus
output [7:0]  count;    // 8-bit counter output
inout        data_bi;   // Bi-directional bus

---

Example: A Simple Module

Here’s a simple 1-bit full adder in Verilog:

module addbit (
  a,    // First input
  b,    // Second input
  ci,   // Carry input
  sum,  // Sum output
  co    // Carry output
);
  // Port declarations
  input a, b, ci;
  output sum, co;
  wire a, b, ci, sum, co;

  // Logic
  assign {co, sum} = a + b + ci;

endmodule

This module can now be reused inside larger modules.

---

Connecting Modules

When using one module inside another, you need to connect ports. Verilog provides two styles:

1. By Order (Implicit)

Ports are connected in the same order as they are declared in the leaf module.

Example – 4-bit adder (using 1-bit addbit):

addbit u0 (r1[0], r2[0], ci, result[0], c1);
addbit u1 (r1[1], r2[1], c1, result[1], c2);
addbit u2 (r1[2], r2[2], c2, result[2], c3);
addbit u3 (r1[3], r2[3], c3, result[3], carry);

Problem: If port order changes in addbit, this breaks. Debugging becomes harder.

---

2. By Name (Explicit)

Here, each port is explicitly named, making the connection order-independent.

Example:

addbit u0 (
  .a   (r1[0]),
  .b   (r2[0]),
  .ci  (ci),
  .sum (result[0]),
  .co  (c1)
);

This style is safer and easier to debug, especially in large designs.

---

Difference Between u0 in Two Cases

• In the adder example, u0 is an instance of another user-defined module (addbit).

• In the parity example, u0 is an instance of a Verilog primitive gate (xor).

Both are instances, but one refers to a custom module while the other refers to a built-in gate.

---

Port Connection Rules

When instantiating modules, remember these rules:

1. Inputs

   • Internally → always type net

   • Externally → can connect to reg or net

2. Outputs

   • Internally → can be net or reg

   • Externally → must connect to a net

3. Inouts

   • Must always be of type net (both internally and externally)

4. Width Matching

   • Allowed to connect signals of different widths, but synthesis may warn

5. Unconnected Ports

   • Allowed (use , or () for explicit unconnected ports)

---

Example: Unconnected Ports

Implicit (order-based):

dff u0 (q, , clk, d, rst, pre); // q_bar is unconnected

Explicit (name-based):

dff u0 (
  .q   (q),
  .d   (d),
  .clk (clk),
  .q_bar (),   // explicitly left unconnected
  .rst (rst),
  .pre (pre)
);

Explicit style is cleaner and avoids confusion.

---

Conclusion

• Modules are the core building blocks in Verilog.

• They communicate with the outside world through ports (input, output, inout).

• Modules can be instantiated by order or by name (explicit style recommended).

• Follow the port connection rules to avoid simulation and synthesis errors.

• Whether it’s a user-defined module like an adder or a primitive gate like XOR, instances allow you to build scalable, hierarchical designs.

Understanding modules is the first step toward mastering Verilog design hierarchy.