VERILOG :4. Hierarchical Identifiers, Nets, Registers, and Strings

Verilog is one of the most widely used Hardware Description Languages (HDL) in digital system design. Whether you are building a simple counter or a complex processor, understanding the building blocks like nets, registers, strings, and hierarchical identifiers is essential.

In this blog, we’ll dive into these concepts with easy-to-follow explanations, practical examples, and diagrams to support learning.

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🔹 1. Hierarchical Identifiers in Verilog

In Verilog, a hierarchical identifier allows you to reference variables, nets, or registers inside lower-level modules from a higher-level module (like the testbench).

👉 Why it matters?
It helps in debugging and monitoring signals deep inside a design without modifying the module code.

Example: Hierarchical Monitoring

module full_adder (
    input a, b, cin,
    output sum, cout
);
  assign {cout, sum} = a + b + cin;
endmodule

module adder_hier;
  wire [3:0] A, B, Sum;
  wire Cout;

  full_adder u0 (A[0], B[0], 1'b0, Sum[0], c0);
  full_adder u1 (A[1], B[1], c0,  Sum[1], c1);
  full_adder u2 (A[2], B[2], c1,  Sum[2], c2);
  full_adder u3 (A[3], B[3], c2,  Sum[3], Cout);
endmodule

module tb;
  reg [3:0] A, B;
  wire [3:0] Sum;
  wire Cout;

  adder_hier U (A, B, Sum, Cout);

  initial begin
    $monitor("At time %0t: tb.U.u0.sum=%b, tb.U.u1.sum=%b",
              $time, tb.U.u0.sum, tb.U.u1.sum);
    A = 4'b1010; B = 4'b0101;
    #10;
  end
endmodule

✅ Here, we accessed tb.U.u0.sum and tb.U.u1.sum using hierarchical identifiers.

📷 Diagram:

• Top module → adder_hier

• Submodules → u0, u1, u2, u3

• Testbench monitors internal sums via hierarchical paths.

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🔹 2. Nets in Verilog

A net represents a connection (wire) between components. Nets don’t hold values by themselves — they just connect outputs to inputs.

Common Net Types

Net Type Meaning wire Default net, carries a continuous value tri Tristate net (used for bus structures) wand Wired-AND (multiple drivers ANDed together) wor Wired-OR (multiple drivers ORed together) trireg Holds last driven value (like a storage net)

Example: Using Different Nets

module net_example;


  wire a, b, c;
  wor w_or;
  wand w_and;

  assign a = 1'b1;
  assign b = 1'b0;

  assign w_or = a;
  assign w_or = b;

  assign w_and = a;
  assign w_and = b;

  initial begin
    $display("WOR result = %b", w_or);   // 1 OR 0 = 1
    $display("WAND result = %b", w_and); // 1 AND 0 = 0
  end
endmodule

📷 Diagram:

• Show wired-OR (multiple signals feeding into one bus with OR).

• Show wired-AND (multiple signals feeding into AND).

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🔹 3. Registers (reg) in Verilog

Unlike nets, registers (reg) hold values. They are updated inside procedural blocks (initial, always).

👉 Remember: reg does not mean hardware register; it simply means a variable that can store a value until reassigned.

Example: Register Usage

module reg_example;
  reg clk;
  reg [3:0] counter;

  initial begin
    clk = 0; counter = 0;
    forever #5 clk = ~clk;  // Clock toggle
  end

  always @(posedge clk) begin
    counter <= counter + 1; // Increment counter
    $display("At %0t, Counter = %d", $time, counter);
  end
endmodule

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🔹 4. Strings in Verilog

Verilog allows string manipulation using arrays of 8-bit ASCII values.

Example: Strings

module string_example;
  reg [8*21:1] str;

  initial begin
    str = "This is sample string";
    $display("String = %s", str);

    // Escape sequences
    $display("Line1\nLine2\tTabbed \"Quote\"");
  end
endmodule

👉 Here, the string is stored as a packed array of 8-bit characters.

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🎯 Conclusion

In this blog, we explored:
✔ Hierarchical identifiers (debugging internal signals)
✔ Nets (wire, wor, wand, tri) and their connectivity roles
✔ Registers (reg) as storage elements updated procedurally
✔ Strings as character arrays with escape sequences

With these foundations, you are ready to move toward Gate-Level Modeling and Simulation, where these primitives come together to form real digital designs.

📌 In the next blog, we’ll cover Gate-Level Modeling in Verilog with primitives and switch-level modeling.