VERILOG 8 : Verilog Operators Explained with Examples

Learning Verilog becomes much easier when you master operators. Just like in C or Java, operators in Verilog help perform mathematical, logical, relational, and bit-level operations. Whether you’re simulating a design or writing RTL code, operators simplify coding and make it more readable.

In this blog, we’ll explore all Verilog operators with clear explanations, syntax, and practical examples.

---

🔹 1. Arithmetic Operators

Arithmetic operators work on numbers (integers, registers, parameters).

Binary Operators: +, -, *, /, %
Unary Operators: +, -

👉 Key Points:

• Integer division truncates fractions.

• Modulus % takes the sign of the first operand.

• If operands contain unknown x, the result is x.

📌 Example:

module arithmetic_operators();
initial begin
  $display (" 5  + 10 = %d", 5 + 10);
  $display (" 10 * 5  = %d", 10 * 5);
  $display (" 10 / -5 = %d", 10 / -5);
  $display (" 10 % 3  = %d", 10 % 3);
  $display (" -5      = %d", -5);
  #10 $finish;
end
endmodule

✅ Output:

5 + 10 = 15  
10 * 5 = 50  
10 / -5 = -2  
10 % 3 = 1  
-5 = -5  

---

🔹 2. Relational Operators

Relational operators compare values.

Operator	Description
<	Less than
>	Greater than
<=	Less than or equal
>=	Greater than or equal

👉 Result:

• 1 if true

• 0 if false

• x if any operand has unknown bits

📌 Example:

module relational_operators();
initial begin
  $display ("5 <= 10 = %b", (5 <= 10));
  $display ("5 >= 10 = %b", (5 >= 10));
  $display ("1'bx <= 10 = %b", (1'bx <= 10));
end
endmodule

✅ Output:

5 <= 10 = 1  
5 >= 10 = 0  
1’bx <= 10 = x  

---

🔹 3. Equality Operators

Two types:

• Logical Equality: ==, != → result may be x

• Case Equality: ===, !== → includes x and z in comparison

📌 Example:

module equality_operators();
initial begin
  $display ("4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001));
  $display ("5 == 10 = %b", (5 == 10));
  $display ("5 != 6  = %b", (5 != 6));
end
endmodule

✅ Output:

4’bx001 === 4’bx001 = 1  
5 == 10 = 0  
5 != 6 = 1  

---

🔹 4. Logical Operators

Used for Boolean conditions.

Operator Description ! NOT && AND
`

📌 Example:

module logical_operators();
initial begin
  $display ("1 && 0 = %b", (1 && 0));
  $display ("1 || 0 = %b", (1 || 0));
  $display ("!1      = %b", (!1));
end
endmodule

✅ Output:

1 && 0 = 0  
1 || 0 = 1  
!1 = 0  

---

🔹 5. Bitwise Operators

Operate bit by bit.

Operator	Description
~	Bitwise NOT
&	AND
`	`
^	XOR
~^ or ^~	XNOR

📌 Example:

module bitwise_operators();
initial begin
  $display ("~4'b0001 = %b", (~4'b0001));
  $display ("4'b1001 & 4'b0001 = %b", (4'b1001 & 4'b0001));
  $display ("4'b1001 ^ 4'b0001 = %b", (4'b1001 ^ 4'b0001));
end
endmodule

✅ Output:

~0001 = 1110  
1001 & 0001 = 0001  
1001 ^ 0001 = 1000  

---

🔹 6. Reduction Operators

Reduce multiple bits into a single bit result.

Operator	Meaning
&	AND
~&	NAND
`	`
`~	`
^	XOR
~^	XNOR

📌 Example:

module reduction_operators();
initial begin
  $display ("&4'b1001 = %b", (&4'b1001));
  $display ("^4'b1001 = %b", (^4'b1001));
end
endmodule

✅ Output:

&1001 = 0  
^1001 = 0  

---

🔹 7. Shift Operators

Operator	Description
<<	Left shift
>>	Right shift

📌 Example:

module shift_operators();
initial begin
  $display ("4'b1001 << 1 = %b", (4'b1001 << 1));
  $display ("4'b1001 >> 1 = %b", (4'b1001 >> 1));
end
endmodule

✅ Output:

1001 << 1 = 0010  
1001 >> 1 = 0100  

---

🔹 8. Concatenation Operator

Combines multiple signals.

📌 Example:

module concatenation_operator();
initial begin
  $display ("{4'b1001, 4'b10x1} = %b", {4'b1001,4'b10x1});
end
endmodule

✅ Output:

100110x1  

---

🔹 9. Replication Operator

Replicates bits multiple times.

📌 Example:

module replication_operator();
initial begin
  $display ("{4{4'b1001}} = %b", {4{4'b1001}});
end
endmodule

✅ Output:

1001100110011001  

---

🔹 10. Conditional Operator

C-like ternary operator:

cond ? expr1 : expr2

📌 Example (Tri-state buffer):

module conditional_operator();
wire out;
reg enable, data;
assign out = (enable) ? data : 1'bz;

initial begin
  enable = 0; data = 1; #1;
  enable = 1; data = 0; #1;
  enable = 1; data = 1; #1;
end
endmodule

✅ Output:

enable=0 → out=z  
enable=1, data=0 → out=0  
enable=1, data=1 → out=1  

---

🔹 11. Operator Precedence

When multiple operators are used, precedence decides execution order.

Precedence Level	Operators
Highest	!, ~, *, /, %
Next	+, -, <<, >>
Then	<, >, <=, >=, ==, !=, ===, !==
Then	`&, &, ^, ^,
Then	`&&,
Lowest	?:

📌 Example:

a = 5 + 3 * 2;  // Multiplication first → result = 11

---

🎯 Final Thoughts

Verilog operators are powerful tools for designing, simulating, and testing hardware systems. From simple arithmetic to bit-level manipulations and conditional logic, they allow concise and efficient code.